1. Field of the Invention
The present invention relates to a semiconductor device comprising an enhancement-mode field-effect transistor and a depletion-mode field-effect transistor, each of which has a heterojunction and uses a two-dimensional electron gas.
2. Description of the Related Art
In order to increase the performance of a computer, it is preferable to increase the operating speed of a semiconductor device and to decrease the power consumption thereof. Therefore, many proposals have been made on transistors made of a compound semiconductor such as gallium-arsenide (GaAs) since the carrier mobility thereof is far greater than that of silicon (Si), which is generally used in current semiconductor devices. In the transistors of a compound semiconductor, field-effect transistors, particularly Schottky barrier-type field-effect transistors, are generally produced since the production process thereof is easier than that of bipolar transistors.
In a field-effect transistor made of GaAs or Si and having a conventional structure, carriers move in a semiconductor crystal in which impurity ions exist. The moving carriers are scattered by the lattice vibration and the impurity ions, whereby the carrier mobility is limited. The lattice scattering effect can be reduced by lowering the temperature, but the ionized impurity scattering effect is not reduced.
It is possible to eliminate the ionized impurity scattering effect by separating the region of carrier movement from the region doped with impurities with the interface of a heterojunction. The combination of the low temperature and the heterojunction increases the carrier mobility so that such a heterojunction-type field-effect transistor can be operated faster than the above-mentioned conventional field-effect transistors.
For example, the heterojunction-type field-effect transistor comprises a semi-insulating GaAs substrate, an undoped GaAs layer (semiconductor channel layer), an N-type aluminum-gallium-arsenide layer (AlGaAs; electron-supply layer), and an N-type GaAs layer (contact layer), which layers are formed in sequence on the GaAs substrate by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method. The undoped GaAs layer and the N-type AlGaAs layer form the heterojunction. The N-type AlGaAs layer has an electron affinity smaller than that of the undoped GaAs layer and contains donor impurities. The N-type GaAs layer and, if necessary, the N-type AlGaAs layer are selectively etched to form a groove for a gate electrode so that a predetermined distance between the top surface of the undoped GaAs layer (i.e., the interface of the heterojunction) and the bottom of the gate electrode is obtained. The distance has an influence on the gate threshold voltage of the field-effect transistor. In the above-mensioned heterojunction-type field-effect transistor, a two-dimensional electron gas is generated in the undoped GaAs layer at the heterojunction interface by transferring electrons into the undoped GaAs layer from the N-type AlGaAs layer and serves as a channel. The electron density of the channel is controlled by an applied voltage of the gate so that the impedance between the source electrode and the drain electrode is controlled.
When a semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor is produced by utilizing the above-mentioned heterojunction-type field-effect transistor, namely, when at least two heterojunction-type field-effect transistors having different gate threshold voltages are produced on the same semi-insulating GaAs substrate by varying a thickness of the N-type GaAs and, if necessary, the N-type AlGaAs under the gate electrodes, it is necessary to form suitable grooves for the gate electrodes by accurately etching the layers formed on the undoped GaAs layer, respectively. However, such etching process is complicated, and accurate etching control is difficult.